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AR# 42820

LogiCORE CPRI v4.1 - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"

Description

Why do I see the following error in BitGen when running theexample design through the ISE 13.2 tools:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow"

Solution

To remove this error, please change the bitgen line in the <core_name>/implement/implement.sh or
<core_name>/implement/implement.bat file to:

bitgen -j -g UnconstrainedPins:Allow -w routed routed mapped.pcf

A bitstream will not be produced. When all I/O pins are placed and constrained to the appropriate I/O standards, the -j and -g UnconstrainedPins:Allow switches can be removed andBitGen will generate a bitstream for download.

For more details on this issue, please see (Xilinx Answer 41615).For Release Notes and Known Issues for the LogiCORE CPRI,please see (Xilinx Answer 36969).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A

Associated Answer Records

AR# 42820
Date Created 09/14/2011
Last Updated 05/20/2012
Status Archive
Type Known Issues