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AR# 42842

7 Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISE 13.1

Description

This answer record discusses the change to the CPLLREFCLKSEL/QPLLREFCLKSEL port definition for 7 Series Transceivers, which causes an issue in simulation in ISE software version 13.1.

Solution

The QPLLREFCLKSEL input port selects GTREFCLK0 or GTREFCLK1 as the reference clock input for the QPLL in the GTXE2_COMMON block.

The CPLLREFCLKSEL input port selects GTREFCLK0 or GTREFCLK1 as the reference clock input for the CPLL in the GTXE2_CHANNEL block.

Please refer to the 'Reference Clock Selection and Distribution' section of the 7 Series FPGA GTX Transceivers User Guide (UG476) for more details on QPLLREFCLKSEL/CPLLREFCLKSEL.

In Virtex-6 FPGA, setting the PLLREFCLKSEL to "000" selects the REFCLK0, however, the definition changed in 7 Series sand the QPLLREFCLKSEL/CPLLREFCLKSEL instead points to "001" to select GTREFCLK0. 

This is the default wizard value in ISE 13.1/13.2 software. 

However, the simulation model released with ISE 13.1 software is still looking for "000", as it is in Virtex-6 FPGA, so the post-layout simulation will not work. 

This does not impact the operation in hardware. 

This simulation issue is fixed in ISE version 13.2 software where the model is updated to "001" matching the wizard setting.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 42842
Date Created 07/05/2011
Last Updated 03/24/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 13.1