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AR# 42844

SPI-4.2 v11.2 (AXI) - Why does the SPI-4.2 Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices

Description


When I generate a Virtex-7 or Kintex-7 device bitstream for the SPI-4.2 v11.2 example design, the following error message occurs:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow."

Solution


Starting in ISE Design Suite 13.2, this error message occurs if any of the pins do not have a location constraint or IOSTANDARD assigned.

For more information about the error message and how to down grade this to a warning message if needed, please refer to (Xilinx Answer 41615).
AR# 42844
Date Created 06/24/2011
Last Updated 06/27/2011
Status Active
Type General Article
IP
  • SPI-4 Phase 2 Interface Solutions