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AR# 42848

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10-Gigabit Ethernet MAC v11.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices

Description

When I generate a Virtex-7 or Kintex-7 device bitstream for the 10-Gigabit Ethernet MAC example design, the following error message occurs:

"ERROR:Bitgen:342-This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent thiserror, it is highly suggested to specify all pin locations and I/Ostandards to avoid potential contention or conflicts and allow proper bitstream creation.  To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you canapply the following bitgen switch: -gUnconstrainedPins:Allow."

Solution

Starting in ISE 13.2 software, this error message occurs if any of the pins do not have a location constraint or IOSTANDARD assigned.

For more information about the error message and how to downgrade this to a warning message if needed, please refer to (Xilinx Answer 41615).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40628 LogiCORE IP 10-Gigabit Ethernet MAC v11.1 (AXI) - Release Notes and Known Issues for ISE Design Tools 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41615 7 Series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" N/A N/A
AR# 42848
Date 05/26/2014
Status Archive
Type General Article
IP
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