UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42850

RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices

Description

When I generate a Virtex-7 or Kintex-7 device bitstream for the XAUI or RXAUI example design, the following error message occurs:

"ERROR:Bitgen:342-This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -gUnconstrainedPins:Allow."

Solution

Starting in ISE 13.2 software this error message occurs if any of the pins do not have a location constraint or IOSTANDARD assigned.

For more information about the error message and how to downgrade this to a warning message if needed, please refer to (Xilinx Answer 41615).

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 42850
Date Created 06/28/2011
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • XAUI
  • RXAUI