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AR# 42882

SPI-4.2 v10.4 - Timing errors encountered when using the 128-bit client interface

Description

In the SPI 4.2 v10.4 and earlier core, occasionally timing errors can be seen when using the example design constraints and a 128-bit user interface.

Solution

The example UCF constraints over-constrains this interface at the full internal core clock rate.  Switching all 128-bit user interface clock constraints to be 3/4 of the internal core clock resolves this issue. The UCF constraints have been updated in v10.5 and later of the SPI 4.2 core.

Linked Answer Records

Master Answer Records

AR# 42882
Date Created 06/28/2011
Last Updated 05/23/2014
Status Archive
Type General Article
IP
  • SPI-4 Phase 2 Interface Solutions