AR# 4292: 4.2i Foundation - Adding schematics to HDL Flow Projects
4.2i Foundation - Adding schematics to HDL Flow Projects
Two flow types exist within Foundation series software: Schematic and HDL. The difference between the flows is not determined by the contents of the project (as either flow can contain a mixture of Schematic and HDL), but by the way in which the designs are processed.
When using the Schematic flow in Foundation projects, you can create a top-level schematic that contains HDL macros. This flow works well, but because underlying HDL modules are synthesized and optimized individually, certain limitations exist.
One drawback is that the design does not benefit from flattening during top-down synthesis optimization. Also, HDL macros in Schematic flows cannot be hierarchical (contain other modules) nor do they have access to user-created VHDL libraries.
To take advantage of cross-boundary optimization and top-down synthesis methodology, use the HDL flow. You are still creating a top-level schematic with underlying HDL modules; however, when this flow is used, the entire design is synthesized and optimized by Foundation Express, and your overall design performance will be improved.
Follow the steps below to combine a top-level schematic (and lower-level schematics) and HDL macros in an HDL flow project.
1. Create a new HDL project. In Foundation Project Manager, select File -> New Project. Be sure to select "HDL" as the flow.
2. Add a schematic library. Because the device family is not selected until the design is synthesized, you must manually add a Xilinx library if you wish to add unified components to your schematics. (If you are simply creating a top-level schematic that will act as a block diagram of the design, this action is not necessary.) Select File -> Project Libraries, choose your target family from the left-hand pane, and click "Add." This library will appear in the Files tab.
3. Open an HDL file from the flow button. Create (or open) an HDL file by clicking on the HDL Editor icon in the Design Entry flow button. In order to create a schematic macro from an HDL file, the file must not be added to the project (i.e., the HDL file does not appear under the Files tab of Foundation Project Manager). If the HDL file has been added to the project, the Create Macro option will not be available. This rule also applies to state machines.
4. Create a symbol for the HDL file. After you have finished editing your HDL file, select Project -> Create Macro. If you are asked for an initial target, you may enter any device at this point. The synthesis that is performed is necessary simply to create the symbol. Repeat steps 3 and 4 for all HDL macros that will be placed directly on the schematic.
5. Edit the schematic. Open Schematic Editor, create a top-level design, and edit this schematic as if you were using the Schematic flow. Xilinx Unified Library components and HDL macros will be available in the Symbols toolbox. You may also create LogiBLOX macros if you wish. Add this schematic to your project by selecting Hierarchy -> Add Current Sheet to Project.
When creating your top-level schematic, you cannot use PAD components (IPAD, OPAD, etc.) from the Xilinx Unified Library. Foundation Express will synthesize this design from the top down and will add ports as well as buffers (if necessary). To define the ports, use Hierarchy Connectors, just as you would if this schematic was at a lower hierarchy level. You may add I/O components such as I/O buffers, I/O flip-flops, or I/O latches, but do not use any PADs.
Save the schematic. HDL files are added to a project when the schematic is analyzed. You will notice that all HDL and ASF files for which schematic macros have been made will be added to the Files tab when the top-level schematic is analyzed.
You may edit the files by opening them from the Foundation Project Manager, but you will only be able to update HDL macros by opening them from the schematic. This must be done to have access to the Project -> Update Macro menu selection.
6. Add lower levels of hierarchy and libraries to your project. If the HDL macros in the schematic have lower levels of hierarchy or use user-defined libraries, these HDL files must be added to the project manually via Document -> Add. Foundation Express must have access to all design files before synthesis.
7. Synthesize the design as you would a top-level HDL project. Click on the Synthesis (or Implementation) Flow button, and select your schematic as the top level. Be sure to select the family that matches the schematic library you have chosen. Foundation Express will link all the project files, and will synthesize the design using the top-down methodology.
- Because the design will be processed by Foundation Express, care must be taken when adding attributes to the schematic. When you add pin location or slew rate constraints, place them on the I/O buffer (or flip-flop or latch), not the net or the hierarchy connector. Other attributes (such as TNMs or Timespecs) are not processed; use a UCF file to apply these constraints. In addition, pin locations, slew rates and certain other design constraints may be placed on the design using the built-in Foundation Express constraints editor.
- When a schematic is added to the project, or when Foundation Express analyzes the schematic portion of the design, the schematic is netlisted into one of three formats: VHDL, XNF, or EDIF. Set the format by selecting Synthesis -> Options and choosing one of the three formats under "Export Schematics To".
- If the design is only a block diagram (there are no unified components), or if no attributes are to be passed from the schematic (including within Xilinx macros), then VHDL should be used. If any attributes have been applied within the schematic, then XNF or EDIF must be selected as the netlist type (EDIF must be used to target Virtex devices).
However, if the schematic includes XNF macros that contain RLOCs, then either VHDL or the "Preserve Hierarchy" option must be selected. This is due to the way that Foundation Express flattens the design; identical RLOCs will exist without hierarchy designations to keep them unique.
1. Create a second project (schematic type) that will be used to create the schematic that you will instantiate in your HDL design.
2. Create the schematic as you would any other lower level of hierarchy, including I/O terminals to define the ports. Unless you plan on instantiating ALL of your user I/O in your design, do not use and IPADs or OPADs in the schematic. Hierarchy is acceptable.
3. After saving the schematic, select Options -> Export Netlist. Do not change the directory, as the .alb file must be seen to write out the netlist. The file name will match the name of the project.
4. Copy the .edn file or .xnf files (there could easily be more than one XNF file) to the HDL project directory. DO NOT ADD THESE FILES TO THE HDL PROJECT.
5. Instantiate the schematic in your HDL file and run it through the HDL flow as you normally would. The synthesis portion of the flow will give "UNLINKED component" warnings, but these may be safely ignored, as this is the standard message for black boxes in Foundation Express.
The "Translate" phase of implementation will read in the EDIF or XNF file(s) when it merges all the portions of your design.