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AR# 42930

12.4/13.4/14.7 MAP-V5:ERROR:Place:1333 - Following IOB's that have input/output programming

Description

When trying to Run a Virtex-5 design, I receive the following errors during map:

ERROR:Place:1333 - Following IOB's that have input/output programming are locked  to the bank 3 that does not support such values
   IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = NR
   List of locked IOB's:
                ADC_C_CLKN
                ADC_C_CLKP
                ADC_D_CLKN
                ADC_D_CLKP 
 

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Solution

In this scenario the pins are locked to bank 3 and they are outputs with the I/O property of LVDS_25.

Pin locks for bank 3 caused the above error:

net                      ADC_C_CLKP           loc = "J7";

net                      ADC_C_CLKN           loc = "J6";

net                      ADC_D_CLKP           loc = "G3";

net                      ADC_D_CLKN           loc = "G1";

Since the pins are locked to bank 3 and they are outputs the error is valid.

This is due to a limitation in the Virtex-5 device where Bank 3 does not allow LVDS outputs.

Only Bank 0 and Bank 1 will allow LVDS outputs.

Workaround:

Change the differential pin locking to either Bank 0 or Bank 1.

net                         ADC_C_CLKP           loc = "N12";

net                         ADC_C_CLKN           loc = "P12";

net                         ADC_D_CLKP           loc = "N10";

net                         ADC_D_CLKN           loc = "P11";

 

Please refer to page 28 of the select I/O resource guide for details:

http://www.xilinx.com/support/documentation/user_guides/ug381.pdf

Details from the datasheet:

LVDS_25Low Voltage Differential Signal:

LVDS_25 is used to drive TIA/EIA644 LVDS levels in a bank powered with 2.5V VCCO.

LVDS is a differential I/O standard. 

As with all differential signaling standards, LVDS requires that one data bit is carried through two signal lines, and it has an inherent noise immunity over single-ended I/O standards. 

The voltage swing between two signal lines is approximately 350 mV. 

The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required.

LVDS requires the use of two pins per input or output. 

LVDS inputs require a parallel termination resistor, either through the use of a discrete resistor on the PCB, or the use of the DIFF_TERM attribute to enable internal termination.

LVDS inputs can be placed on any I/O bank, while LVDS outputs are only available on I/O banks 0 and 2.

LVDS_33Low Voltage Differential Signal:

LVDS_33 is used to drive TIA/EIA644 LVDS levels in a bank powered with 3.3V VCCO.

Electrically the same as LVDS_25. 

LVDS inputs require a parallel termination resistor, either through the use of a discrete resistor on the PCB, or the use of the DIFF_TERM attribute to enable internal termination. 

LVDS inputs can be placed on any I/O bank, while LVDS outputs are only available on I/O banks 0 and 2.

 

AR# 42930
Date Created 06/30/2011
Last Updated 10/02/2014
Status Active
Type Design Advisory
Devices
  • Virtex-5 LX
Tools
  • ISE Design Suite - 13.3
  • ISE Design Suite - 14
  • ISE Design Suite - 12