UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42933

13.1 Route: ERROR:Route:541 - Following pins have illegal PLL clocks, SPARTAN

Description

PAR is reporting the following error in during routing. Why does this error occur?

ERROR:Route:541 -
Following pins have illegal PLL clocks
Pin:CLK1.OLOGIC_X1Y1
Pin:CLK1.OLOGIC_X9Y1
Pin:CLK1.OLOGIC_X8Y3
Pin:CLK1.OLOGIC_X10Y3
Pin:CLK1.OLOGIC_X9Y3
Pin:CLK1.OLOGIC_X11Y3
Pin:CLK1.OLOGIC_X12Y3
Pin:CLK1.OLOGIC_X10Y1

Solution

This may occur because a BUFPLL is being used to drive a PLL clock to an ODDR in the PAD. This is not permitted; an OSERDES needs to be used instead. However, depending on the clock frequency of the PLL clock being used it may be possible to connect to the PAD via a BUFG.
AR# 42933
Date Created 07/13/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2