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AR# 42977

MIG Virtex-6 DDR3 - Efficiency at BC4 (Burst Chop 4) Mode

Description

What about efficiency at BC4 mode? Is it proper for high-volume data transfer?

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Due to the 8n-prefetch architecture of DDR3, one burst must be 8 bits. Burst chop 4 (BC4) mode uses internal control signals to select only the first 4 bits of data to read or write. So, the entire command excution time for BL8 and BC4 is the same. If you are using a valid data cycle and total clock cycle to calculate efficiency, BC4 has a very low efficiency (lower than 50%). For a large data transfer and high-bandwidth application, BC4 is not suitable. For maximum efficiency, please run the actual data pattern simulation as described in (Xilinx Answer 36719).

Linked Answer Records

Associated Answer Records

AR# 42977
Date Created 07/07/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
IP
  • MIG