UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 43042: MIG all version all FPGA DDR3 - File can not be accessed during simulation

AR# 43042

MIG all version all FPGA DDR3 - File can not be accessed during simulation

Description

After I Define MAX_MEM in a DDR3 simulation model and run simulation, the following message is reported and simulation quits.

Failed to open file "/tmp/sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.open_bank_file.0"

 

Solution

This message has been seen in 7 series MIG1.2.

Virtex-6 and Spartan-6 also have the same problem.

The issue happens because "tmp_model_dir" in the DDR3 simulation model is set to "/tmp".

In windows, "/tmp" is not a valid folder path.

Once this is changed to a valid path, no simulation issues occur.
AR# 43042
Date 08/07/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Spartan-6 LX
  • Spartan-6 LXT
  • More
  • Spartan-6Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Less
IP
  • MIG

By using this website, I accept the use of cookies.   Learn more

Page Bookmarked