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AR# 43131

CORE Generator - Using Design Entry set to Schematic symbols are not created correctly from within CORE Generator

Description

After setting the "Design Entry" setting for CORE Generator project to "Schematic" and generating an IP core. It does not appear that the schematic symbol is generated correctly.

After adding the generated core by way of XCO to an ISE project, the Symbol can be very large in some cases and the data buses are not labeled at all as they should be.

Solution

In cases where theschematic symbol is not created, or created as desired during core generation,a new symbol can be generated as follows.

  • Add the VHDL/Verilog wrapper file into the ISE project and create a schematic for that file from within ISE. This creates a sensible size schematic with data buses labeled as expected.

AR# 43131
Date Created 12/21/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • Less