The following DRC error is reported by BitGen:
"ERROR:PhysDesignRules:2066 - Component xxxxxx is
configured for ISERDESE1. A routethru from the /ILOGIC_XmYn/DDLY to
/ILOGIC_XmYn/O pins, configuring a second input path for the DDLY pin is in
conflict with ISERDESE1 configuration."
Howcan Iresolve this error?
Thiserror occursbecause the DDLY to O routethru in the ISERDESE1 component is used, butconflicts with the ISERDESE1 configuration.WhenISERDESE1is in use and the D pin is used for the sequential data input, the DDLY to O routethru is only available with IOBDELAY attribute of ISERDESE1 set to "BOTH".
To resolve this error, change the IOBDELAY attribute of ISERDESE1 to "BOTH".
Note: When the sequential data input goes into not only the D pin ofISERDESE1, but also other components such as output pads, slices, MMCM, and so on,the DDLY to O routethru will be used because of the routing resource limitation.