AR# 432: How flip-flop initial states are determined
How flip-flop initial states are determined
In XEPLD schematic designs, you cannot specify preload values on a flip-flop by flip-flop basis without disabling preload optimization. The preload states of the various registers depend upon where they get mapped in the XC7000 architecture:
* HDFB: preloadable to VCC or GND (default is GND)
* FFB: preloads to VCC in all 7000 devices, except for 7336 and 7318, which can preload to VCC or GND (default is GND)
* INPUT PAD REGISTERS (7300, 7236/A): preload to VCC,
7272: undefined for input pad registers, all other flip-flops have preload value of 0.
The Unified library components have specified preload values defined within each component's underlying PLUSASM description. The preload value depends on where the register is mapped into the device architecture as defined above.
If you are depending on having consistent preload values being output from the Fitter, you must set the PRELOAD_OPT attribute for the design to OFF. Doing this prevents the software from optimizing functions that could be mapped into fast function blocks (FFBs), mapped into input registers, or optimized in some other way. If PRELOAD_OPT is ON (this is the default setting), registers can be mapped to any location in the device.
In the pre-Unified library, all flipflops had preload values of 0 except for input pad registers, and these preload values did not change because the logic did not get optimized.
In version 5.0, there is no software support for initializing specific flipflops to known values. This capability has been added in the 5.1 release via the INIT attribute (attach INIT=R to a flip-flop to preload to GND, and INIT=S to preload to VCC)
Also, if you use a register that only has a CLR pin, it will not be mapped to an input register or fast function block (FFB) if preload optimization is disabled.