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AR# 43210

Timing - How do I disable expected setup and hold time violations that are due to data synchronization between clock domains while using CORE Generator FIFO?

Description

In a design that contains CORE Generator FIFO, you can see setup and hold timing errors on cross-clock domain paths within the FIFO core under period constraints analysis or the unconstrained paths analysis.

When generating a FIFO with independent clock domains (whether a DCM is used to derive the write/read clocks or not), the core internally synchronizes the write and read clock domains. For this reason, setup and hold time violations are expected on certain registers within the core. The core is designed to properly handle these conditions, regardless of the phase or frequency relationship between the write and read clocks. Therefore, these cross-clock domain paths can be ignored during timing analysis.

How do I disable expected setup and hold time violations due to data synchronization between clock domains while using CORE Generator FIFO?

Solution

There are two ways to disable these expected setup and hold time violations that are due to data synchronization between clock domains:

Add the following constraint to your design this constraint sets a timing constraint to the synchronization logic by requiring a maximum set of delays. The maximum delays used is defined by 2x of the slower clock period.

NET <fifo_instance>/grf.rf/gcx.clkx/wr_pntr_gc<0> MAXDELAY = 12 ns;
NET <fifo_instance>/grf.rf/gcx.clkx/wr_pntr_gc<1> MAXDELAY = 12 ns;
...
NET <fifo_instance>/grf.rf/gcx.clkx/wr_pntr_gc<9> MAXDELAY = 12 ns;
NET <fifo_instance>/grf.rf/gcx.clkx/rd_pntr_gc<0> MAXDELAY = 12 ns;
NET <fifo_instance>/grf.rf/gcx.clkx/rd_pntr_gc<1> MAXDELAY = 12 ns;
...
NET <fifo_instance>/grf.rf/gcx.clkx/rd_pntr_gc<9> MAXDELAY = 12 ns;

Add the following constraint to your design this constraint directs the tool to ignore the appropriate paths that are part of the synchronization logic:

NET <fifo_instance>/grf.rf/gcx.clkx/wr_pntr_gc<0> TIG;
NET <fifo_instance>/grf.rf/gcx.clkx/wr_pntr_gc<1> TIG;
...
NET <fifo_instance>/grf.rf/gcx.clkx/wr_pntr_gc<9> TIG;
NET <fifo_instance>/grf.rf/gcx.clkx/rd_pntr_gc<0> TIG;
NET <fifo_instance>/grf.rf/gcx.clkx/rd_pntr_gc<1> TIG;
...
NET <fifo_instance>/grf.rf/gcx.clkx/rd_pntr_gc<9> TIG;

If distributed RAM FIFO is used, the following constraints may also be required to improve the timing.

INST <fifo_instance>/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/Mram* TNM= RAMSOURCE;
INST <fifo_instance>/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout* TNM= FFDEST;
TIMESPEC TS_RAM_FF= FROM RAMSOURCE TO FFDEST <<one read clock period>> DATAPATHONLY;

Please refer to "Setup and Hold Time Violations" section in the FIFO Generator User Guide (UG175):
http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator_ug175.pdf

AR# 43210
Date Created 12/05/2012
Last Updated 12/05/2012
Status Active
Type Known Issues
Tools
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