This article describes an axi_ethernetlite core issue that introduces a map error:
How do I resolve this error?
In the MPD file of axi_ethernetlite, the ports 'PHY_tx_clk' and 'PHY_rx_clk' have the option of 'BUFFER_TYPE = IBUF'.
This option inserts IBUFs onto the two ports of the core netlist during synthesis.
If the external ports for these clocks are connected with other module of the same EDK project, there will be a map error "ERROR:LIT:514."
This exists in 13.2 software because of the XST issue where "buffertype=ibuf does not insert IBUF when XST property iobuf=no".
The workaround is to make this core a local one and to delete the 'BUFFER_TYPE = IBUF' option in MPD.
This issue is currently scheduled to be fixed in the 13.3 EDK software release.