GTX Transceiver Attribute Updates for Initial Engineering Sample (ES) Silicon
The next table shows the attribute updates that you must make to the GTX wrapper generated by the 7 series FPGA Transceiver Wizard to ensure reliable operation for the Initial ES silicon.
Note: The ISE Design Suite 13.3 generates these attribute updates natively when you use v1.5 of the 7 series FPGA Transceiver Wizard.
However, for these attribute updates to be generated correctly, make sure to select the correct part/package/speed grade combination to enable the Initial ES option under "Silicon Revision" in the Wizard GUI.
The Initial ES support in this tool/wizard release is only for the following:
In ISE Design Suite 13.4, v1.5 of the 7 series FPGA Transceiver Wizard generates settings for Initial ES silicon only and v1.6 supports the General ES silicon only.
The bit streams for Initial ES cannot be used on General ES silicon and vice versa.
The updated v1.5 (v1.5 Rev 1) in ISE Design Suite 13.4 generates updated RXCDR_CFG values based on divider and PPM settings.
The newer Wizard version v1.5 Rev2 in ISE 14.2/Vivado 2012.2 design tools also supports the Virtex-7 XC7V2000T Initial ES devices.
64'h0000040000001000 for Virtex-7
<+/- 300 ppm: 72'h1107FE406001040000
<+/- 700 ppm:72'h1107FE406021040000
<+/- 1000 ppm:72'h1107FE206021040000
<+/- 300 ppm: 72'h1107FE406001100000
<+/- 700 ppm: 72'h1107FE406021100000
<+/- 1000 ppm: 72'h1107FE206021100000
TXOUTCLK and RXOUTCLK Ports Restrictions and Use Cases
There are some restrictions in using TXOUTCLK and RXOUTCLK for the Initial ES silicon.
The following rules must be followed for proper operation of TXOUTCLK and RXOUTCLK:
RXOUTCLKSEL must be set to 3'b000 when RXOUTCLK is not used to output the clock and TXOUTCLKSEL must be set to 3'b000 when TXOUTCLK is not used to output the clock.
The following are some suggested use cases to implement designs to satisfy the above requirements:
TX Buffer Enabled Case
When TX buffer is used, use output of IBUFDS_GTE2 to route the GTX transceiver reference clock to fabric clocking resources.
RX Buffer Enabled Case
When RX elastic buffer is used, RXOUTCLKSEL of that lane must be set to 3'b000. If RX recovered clock must be routed out to the fabric, the clock routing should be planned carefully considering TXOUTCLK usage in mind.
Buffer Bypass Case
QPLL Use Mode and Work-around
To ensure that the QPLL frequency band has optimal margin across Voltage and Temperature variations, the attached coarse calibration module "qpll_cal.v" must be incorporated in the user design.
An example instantiation of this module is provided in the file "qpll_fix_top.v".
This module is included in the v1.5 of 7 Series FPGA Transceiver Wizard in ISE Design Suite 13.3.
Receiver Link Margin/Equalization Selection
The receiver can have a reduction in jitter tolerance when used in full-rate mode (RXOUT_DIV = 1).
It is recommended where possible to always use data rates where RXOUT_DIV = 2, 4, 8.
This applies to both CPLL and QPLL.
The 7 Series GTX receiver has two different modes of adaptive equalization called Low-Power Mode (LPM) and Decision Feedback Equalization (DFE) mode.
For more details, please refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
The GTX receiver can support a channel with 12 dB loss at 6.6 Gb/s in both LPM and DFE modes.
This is assuming PRBS31 data pattern and a TX launch amplitude of 850 mV Vp-p, diff, TX pre-cursor emphasis of around 2 dB and TX post-cursor emphasis of around 4 dB.
GTX Software Use Model Changes
For software use model changes and requirements for 7 series GTX transceivers, refer to (Xilinx Answer 43339).
09/06/2012 - Fixed minor typos and corrections.
01/12/2012 - Updated RXCDR_CFG settings for different PPM scenarios.
12/12/2011 - Updated the table with a note on RXCDRLOCK port.
11/09/2011 - Added a note on supported Initial ES device combinations in v1.5 of the Wizard in ISE 13.3.
10/27/2011 - Added Wizard/ISE version information that includes the fixes.
10/17/2011 - Updated RXCDR_CFG to include values for both full-rate and half-rate.
08/25/2011 - Updated title to include Virtex-7 FPGA. Updated the table with BIAS_CFG setting for Virtex-7 FPGA.
08/16/2011 - Minor edits.
07/28/2011 - Initial release.