This is incorrect behavior as internal VREF should be applied to all banks that require VREF. To work around the problem, add the INTERNAL_VREF constraint into the generated UCF for the missing banks.
Example 1: INTERNAL_VREF for Bank 14 using HSTL_II (1.5V), which requires a 0.75V reference voltage, uses the following constraint:
CONFIG INTERNAL_VREF_BANK14 = 0.75;
This is scheduled to be fixed in the 13.3 release.
For Internal/External VREF Guidelines, see (Xilinx Answer 42036).
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
41227 | MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
42036 | MIG 7 Series - Internal/External VREF Guidelines | N/A | N/A |
41227 | MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 | N/A | N/A |
AR# 43250 | |
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Date | 05/20/2012 |
Status | Active |
Type | Known Issues |
Devices | |
Tools | |
IP |