UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43259

13.x Virtex-6 GTH IBERT - Problems running half rate speed with the IBERT core

Description

For the Virtex-6 GTH IBERT core, if you run the transceiver at half rate (PLL output divider = 2)or quarter rate(PLL output divider = 4), the core does not run at thecorrect half or quarter rate specified. TheAnalyzerGUIstates thatyou are running at the correct rate. However, if you measure theTX pins with an oscilloscope, the line rate is not correct and is stillat the full rate speed (PLL output divider = 1).

Solution

For 13.2 and earlier, the Virtex-6 GTH IBERT core does not set the TX_CFG2_LANEx attribute to the correct setting. This causes the GTH not run at the desired line rate.

Follow these instructions to modify the attribute to thecorrect value:

  1. Click on the DRP TAB in theIBERT GUI in ChipScope analyzer.
  2. Find the TX_CFG2_LANEx attribute.
  3. If you are using a PLL output divide setting of 1 (full rate), then the TX_CFG2_LANEx attribute should be set to 0x0081. If you are using a PLL output divide setting of 2 or 4 (half rate or quarter rate), the TX_CFG2_LANEx should be set to 0x0001.

This issue is to be fixed in the 13.3 ISE Design Suite.

AR# 43259
Date Created 07/25/2011
Last Updated 01/02/2013
Status Active
Type Known Issues
Devices
  • Virtex-6 HXT
Tools
  • ChipScope Pro - 13.1
  • ChipScope Pro - 13.2