AR# 4328: Exemplar - How do I initialize RAM or ROM in VHDL code?
AR# 4328
Exemplar - How do I initialize RAM or ROM in VHDL code?
Description
Keywords: Initialize, INIT, RAM, ROM, VHDL
Urgency: Standard
General Description: I have either inferred or instantiated RAM or ROM in my HDL code. How can I initialize the RAM/ROM contents to a known value so that after programming the part, the memory element will contain a predetermined value?
Solution
1
Following are VHDL and Verilog examples.
Note: After processing the design through the Xilinx tools, when verifying the RAM/ROM contents in EPIC the INIT, the value may appear different than the one that was originally given. This is possible because PAR is given the availability to move the address lines for better routability; because of this, the INIT value will change accordingly.
-- VHDL example -- Ram instantiation and initialization
This example shows how to create a 16x4s RAM using Xilinx RAM16x1S component.
library IEEE; use IEEE.std_logic_1164.all;
entity ram_16x1s is generic (init_val : string := "0000" ); port (O : out std_logic; D : in std_logic; A3, A2, A1, A0: in std_logic; WE, CLK : in std_logic); end ram_16x1s;
architecture xilinx of ram_16x1s is
attribute INIT: string; attribute INIT of u1 : label is init_val;
component RAM16X1S is port (O : out std_logic; D : in std_logic; WE: in std_logic; WCLK: in std_logic; A0: in std_logic; A1: in std_logic; A2: in std_logic; A3: in std_logic); end component;
begin
U1 : RAM16X1S port map (O => O, WE => WE, WCLK => CLK, D => D, A0 => A0, A1 => A1, A2 => A2, A3 => A3);
end xilinx;
library IEEE; use IEEE.std_logic_1164.all; --use IEEE.std_logic_unsigned.all;
entity ram_16x4s is port (o: out std_logic_vector(3 downto 0); we : in std_logic; clk: in std_logic; d: in std_logic_vector(3 downto 0); a: in std_logic_vector(3 downto 0)); end ram_16x4s;
architecture xilinx of ram_16x4s is
component ram_16x1s generic (init_val: string := "0000"); port (O : out std_logic; D : in std_logic; A3, A2, A1, A0 : in std_logic; WE, CLK : in std_logic); end component;
begin
U0 : ram_16x1s generic map ("FFFF") port map (O => o(0), WE => we, CLK => clk, D => d(0), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3)); U1 : ram_16x1s generic map ("ABCD") port map (O => o(1), WE => we, CLK => clk, D => d(1), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3)); U2 : ram_16x1s generic map ("BCDE") port map (O => o(2), WE => we, CLK => clk, D => d(2), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3)); U3 : ram_16x1s generic map ("CDEF") port map (O => o(3), WE => we, CLK => clk, D => d(3), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));
end xilinx;
2
-- Verilog
This example shows how to create a 16x4 RAM using Xilinx RAM16X1S component.
// Only for Simulation -- the defparam will not synthesize // Use the defparam for RTL simulation. // There is no defparam needed for Post P&R simulation.