AR# 4331: Exemplar: How to force some outputs FAST and some SLOW
AR# 4331
Exemplar: How to force some outputs FAST and some SLOW
Description
Keywords: outputs, slow, fast
Urgency: Standard
General Description:
Using Leonardo I want to force some of my outputs FAST while keeping some SLOW. How can I do this since there is only an option to make all outputs FAST?
Solution
1
The best way to make some outputs FAST and some outputs SLOW is to turn OFF the Optimize option to Use Fast Output Buffers, then use the set_attribute command to force the desired outputs to FAST. Leaving all outputs FAST can cause ground bounce.
To force an output fast do the following:
1) After 'Read' use the set_attribute command
set_attribute -port Q_out -name FAST set_attribute -port data_out -name FAST
2) In Optimize->Advanced, make sure the option 'Use Fast Output Buffers' is De-selectecd.
3) Optimize
4) write out the Edif netlist.
The set_attribute can also be used in a tcl script after 'Read'.
2
Setting an output to FAST in your VHDL code: ------------------------------- library IEEE; use IEEE.std_logic_1164.all;
entity d_register is port (CLK, DATA: in STD_LOGIC; Q: out STD_LOGIC);
attribute FAST : string; attribute FAST of Q : signal is "";
end d_register;
architecture BEHAV of d_register is
begin
My_D_Reg: process (CLK, DATA) begin if (CLK'event and CLK='1') then Q <= DATA; end if; end process; -- End My_D_Reg