AR# 43344


MIG 7 Series DDR3/DDR2 - Dynamic Calibration and Periodic Read Behavior


The MIG 7 series DDR3/DDR2 design includes two dynamic calibration features to ensure maximum data capture margin over voltage and temperature. The dynamic calibration is performed during each read within the Phaser_IN to continually adjust as required. When the bus is idle or performing writes and a read is not executed within one microsecond, a periodic read is performed to prepare for subsequent reads. This answer record details the dynamic calibration and periodic read behavior within the MIG 7 series DDR3/DDR2 design.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The Phaser_IN performs two dynamic adjustments during reads. The first is within the Phaser_IN DLL which needs to see DQS edges to keep the free-running frequency reference clock phase align locked to the associated read DQS. This dynamic adjustment only looks at the DQS edges and makes adjustments as required. The internal clock is used at the end of the burst when there are no more DQS edges, but clocks are needed to get the final data through the ISERDES.

The second dynamic adjustment is performed within the Phaser_IN to fine tune the position of the DQS preamble for the subsequent read. This dynamic adjustment only looks for the DQS preamble. It is needed to account for drift in the system which can move the DQS with respect to the internal clock.

Both of these Phaser_IN dynamic adjustments require periodic reads to ensure the Phaser_IN is continually adjusted and ready for reads. Because of this, the MIG 7 series DDR3/DDR2 controller sends periodic reads every one microsecond when the bus is idle or performing writes. The Phaser_IN only requires read DQS. Therefore, if reads are being performed as requested from the user interface, the controller will not send the periodic reads. When the controller is writing and the one microsecond periodic reads are due, the reads are sent to the address of the next read/write in the queue. When the controller is idle and no reads or writes are requested, the periodic reads will use the last address accessed. If this address has been closed, an activate will be required. Two back-to-back BL8 reads are required for the dynamic alignment.

All of the dynamic adjustment is hard logic. However, the periodic reads sent to look at DQS is soft logic controlled by the MIG 7 series DDR3/DDR2 controller. Customers using the PHY only design MUST include the periodic read logic within the custom controller.

If the periodic reads are not included, two things will happen that can cause problems:

  • The free running Phaser_IN ICLK will drift away from DQS. This exposes the memory system to issues when ICLK switches.
  • Read latency adjustments will not be done within the Phaser. This can cause issues with the switching logic in the Phaser_IN.

The periodic read was added in MIG v1.5, released with ISE Design Suite 14.1. Further characterization work proved the one microsecond periodic read was required to keep the Phaser_IN aligned and ready for subsequent reads. The frequency of the periodic reads MUST be one microsecond and cannot be changed.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51954 MIG 7 Series DDR2/DDR3 - PHY Initialization and Calibration N/A N/A
AR# 43344
Date 02/05/2013
Status Active
Type Solution Center
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