Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Driving Write on the User Interface
The write path of the User Interface uses a simple 64-deep FIFO structure to hold data in preparation for a Write transaction to memory. The full flag (pX_wr_full) from the Write Data FIFO must be Low for new data to be accepted into the FIFO when pX_wr_en is asserted during the rising edge of pX_wr_clk. Otherwise, the data is ignored. If the full flag is Low, the pX_wr_data bus is captured into the FIFO on the rising edge of pX_wr_clk. For every clock cycle that pX_wr_en is asserted, there must be valid data on the pX_wr_data bus.
The count signal bus (pX_wr_count) provides a count of the number of entries in the FIFO. Due to the asynchronicity of the FIFOs in the MCB, the count signal bus has a longer latency than the empty and full flags. Therefore, this bus should only be used for intermediate references and watermarks.
To implement a Write transaction, the Write Data FIFO first must be loaded with sufficient data to complete the request as dictated by the burst length value that is entered into the Command FIFO. Otherwise, an underrun condition occurs when the transaction tries to execute.
For timing diagrams and more information, see UG388 under "MCB Operation > Memory Transactions > Simple Write".