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AR# 43357

MIG Spartan-6 MCB - Supported DDR Commands

Description

This section of the MIG Design Assistant focuses on the available DDR Commands that you can run for the Spartan-6 Memory Controller Block(MCB) design. Below you will find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The pX_cmd_instr [2:0] signal is used to designate the requested command.The Spartan-6 FPGA MCB design allows reads, writes, and refreshes to be requested from the user/native interface.

Operation Code
Read 001
Write 000
Read with Auto Precharge 011
Write with Auto Precharge 010
Refresh 1xx


Based on the command and address requested by the user, the MIG design executes all required commands, that is,activates, precharges, and so on with appropriate timing to adhere to the JEDEC standard.

For a complete list of the User Interface command signals and their functions, see UG388 under "MCB Functional Description > Interface Details > User (Fabric Side) Interface > Command Path".

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43323 MIG Spartan-6 MCB - Driving the User Interface N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43441 MIG Spartan-6 MCB - Controller Responsibilities N/A N/A
43323 MIG Spartan-6 MCB - Driving the User Interface N/A N/A
AR# 43357
Date Created 08/22/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG