This part of the MIG Design Assistant guides you to information on addressing at the user interface.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
From the user interface perspective, the MCB provides a simple and sequential byte addressing scheme into the physical DRAM. The fact that DRAMs store data in fixed segments is abstracted by this scheme, allowing for a simple SRAM-like address interface. The MCB automatically converts the user interface byte address into the necessary row, bank, and column address signals required for a particular memory device configuration.
Address Requirements for Byte Address Alignment
The byte address presented to the user interface must be aligned to the port width. Depending on the number of bytes in the port width, a certain number of the low address bits must be set to 0 to ensure that consecutive addresses fall on data word boundaries. For more information, see the following table.
The write data mask inputs (pX_wr_mask) to the user interface can be used to offset the starting address byte location; see(Xilinx Answer 43358).
Byte Address to Memory Address Conversion
The memory standard, bus width, and density all affect how the user interface byte address bits map to the respective row, bank, and column address bits. Memory device selection in the MIG tool results in the passing of the necessary parameters to the MCB so that it can create the proper address bit assignments.
The MCB supports two general schemes for mapping the user interface byte address to the memory interface physical address: ROW_BANK_COLUMN and BANK_ROW_COLUMN.
For more information on address mapping, see the Spartan-6 FPGAMemory Controller User Guide(UG388), under "MCB Operation" -> "Byte Address to Memory Address Conversion": http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
DDR2/DDR3 Burst Wrapping
DDR2 memories implement a 4n-prefetch internal bus, which allows the SDRAMs internal array to be accessed by a bus that is four times wider than the external bus. For example, a 16-bit wide DDR2 memory uses a 64-bit wide internal bus to access the core array. The prefetch architecture takes this 64-bit fetch and loads it into four 16-bit prefetch buffers. During the DDR2 burst cycle these four registers are selected by the column addresses.
DDR3 memories implement a 8n-prefetch internal bus, which allows the SDRAMs internal array to be accessed by a bus that iseight times wider than the external bus. For example, a 16-bit wide DDR3 memory uses a 128-bit wide internal bus to access the core array. The prefetch architecture takes this 128-bit fetch and loads it intoeight 16-bit prefetch buffers. During the DDR3 burst cycle these eight registers are selected by the column addresses.
The MCB always starts reads and writes at the burst boundaries ofthe memory.Therfore, the burst order for a write with BL=8 will always start at column address 0 and count up sequentially to 7. While for a BL=4, the starting column address will either be 0 (A3 = 0) or 4 (A3 = 1). For more details on burst addressing see the appropriate JEDEC spec. If the user interface specifies a burst address that falls outside of the burst boundaries of the memory, the MCB will mask the data appropriately.
32-bit User Interface
x16-DDR3 SDRAM(For DDR3MCB only supports BL8)
For a 32-bit User Interface pX_cmd_addr[1:0]must be 2'b00. Since theUser Interface uses byte addressing, every two addresses on the user interface correspond to one address in the x16 DDR3 column address space.
pX_cmd_addr[2:0] = 3'b100
pX_cmd_bl[5:0] = 5'b0_0000 (1 32-bit word burst)
pX_cmd_instr[2:0] = 3'b000
This tranlates to the following writes atthe x16 DDR3 memory:
|lower 16 bits of data|
|upper 16 bits of data|