This can be seen when using an incorrect CLK setup for the DDR register. The supported clocking options follow. These options are from page 31 of the Spartan-6 FPGA Clocking Resources User Guide, v1.6 (UG382):
DDR Data Rate (IDDR2, ODDR2, No IOSERDES2)
The following options can be used for clocking IDDR2 and ODDR2 primitives.
- When performance is not critical, use a single DCM output to drive both clock (C0) and the inverted clock (C1) using local inversion. Works with or without IODELAY2.
- For the highest performance, use two DCM outputs with separate BUFGs with 180 phase difference. Works with or without IODELAY2. See Figure 1-18.
- If not using a DCM, then the GCLK input should directly drive two BUFIO2s. Use two BUFIO2s with the first BUFIO2 (USE_DOUBLER) for C0 and an inverted clock using BUFIO2 (I_INVERT = TRUE) for C1 connected to the same GCLK. FPGA logic is driven by BUFG (C0 BUFIO2-DIVCLK). There is a routing delay through the BUFG.
- Using an IODELAY2 requires the IBUFGDS_DIFF_OUT. (See Figure 1-35, page 51).
- A single-ended input with IODELAY2 is not supported.
- For bidirectional interfaces, input and output logic must both use the same data rate (IDDR2 and ODDR2). Mixing SDR and DDR bidirectional I/Os are not permitted.
You need to modify your design to match these criteria. In a future release,the MAP or PAR software will flag thisissueto prevent a rerun of the full implementation flow.