We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43372

MIG 7 series v1.2-v1.4 DDR3 - DQS Preamble is not always detected correctly for XC7K325T Initial Engineering Sample


The XC7K325T Initial Engineering Sample (ES) silicon does not always detect the DQS Preamble correctly for theMIG DDR3 interfaces. This is not dependent on the maximum frequency, but rather on certain frequency ranges which can vary depending on the DRAM and PCB timing.


The work-around is to implement an enhanced calibration algorithm, which performs a series of quick tests with varying loop delays and then chooses the safest operating point. The CK clock to the memory is delayed during this time. Proper detection of the DQS Preamble has been verified in the Kintex-7 General Engineering Sample (ES) silicon revision and the enhanced/extended calibration is not needed.

Failure to detect the DQS Preamble occurs in bands of frequencies that vary across process. While the enhanced/extended calibration algorithm is expected to support most valid DDR3 operating frequencies, moving to a different frequency might be required in some instances for proper interface operation. Additionally, as the extended calibration is performed once, self-heating on the DRAM or FPGA could cause lead to data errors. Resultant data errors from the missing DQS preamble are seen as a byte lanes shift(s). The first byte or two will be missing and the remaining will be shifted.

The enhanced calibration can take approximately one minute to complete calibration upon each configuration or reset.

ISE Design Suite 13.4

  1. Generate the target memory interface design using MIG 7 Series 1.4
  2. Install the required BitGen Patch for Kintex-7 325T Initial Engineering Sample (ES) Devices; see(Xilinx Answer 43060).
  3. Manually modify the following top-level parameters
    1. Set "XC7K325T_REV_1X" to "TRUE".
      This parameter enables the extended calibration circuit which chooses the safest operating point as noted above.
    2. Set PART_REV to "325t.1".
      This parameter properly configures the PHASER_IN parameters for the Kintex-7 325T Initial Engineering Sample Devices.

NOTE: To prevent long simulation run times, SIM_BYPASS_INIT_CAL = "OFF" is not supported in simulation.


TheXC7K325T_REV_1X must be enabled via C_XC7K325T_REV_1X = TRUE, which enables the enhanced calibration.

ThePART_REV is specified by the axi_7series_ddrx's parameter C_PART_REV =325t.1 in the MHS file.

TheC_PART_REV parameter was introduced with the HW_VER = 1.03.a of theaxi_7series_ddrx and does not exist on previous versions.

Seethe EDK Initial ES Enhanced Calibration Considerations section below.

CORE Generator MIG

For 13.3 MIG 7 Series v1.3 and 13.4 MIG 7 Series v1.4 users, the enhanced calibration is included in the MIG 7 Series v1.3-v1.4 designs but must be turned on using the XC7K325T_REV_1X parameter as described above.

EDK Initial ES Enhanced CalibrationConsiderations

Do not access the AXI_7Series_DDRx peripheral via XMD until calibration has completed, due to a time-out behavior in XMD. The port init_calib_complete is available as a calibration completion signal, which is desirable to connect to a LED or a GPIO peripheral to signify to the user that XMD can now access memory.

Due to the long calibration time, it might also be desirable to minimize XMD resets during debugging. The following commands prevent XMD from performing resets during other commands (issued after the "connect mb mdm" command) :

  • XMD% debugconfig -reset_on_run disable
  • XMD% debugconfig -reset_on_data_dow disable

Watchdog timers might also need to be extended or disabled during extended calibration to prevent continual reset failures. For most other design uses, no special handling is necessary as AXI READY signalsdo notallow for forward progress during calibration.

ISE Design Suite 13.3

You must manually turn on the XC7K325T_REV_1X top-level parameter to TRUE. Set this parameter only when using XC7K325T 1.X silicon and to enable the enhanced calibration.

NOTE: To prevent long simulation run times, SIM_BYPASS_INIT_CAL = "OFF" is not supported in simulation.


For 13.3 EDK AXI_7Series_DDRx users, the enhanced calibration requires an additional patch. Extract the following patch into the project pcore/ directory:http://www.xilinx.com/txpatches/pub/applications/misc/ar43772_13.3_edk.zip.

Seethe EDK Initial ES Enhanced Calibration Considerations section below.

ISE Design Suite 13.2

For 13.2 MIG 7 series v1.2 users, the enhanced calibration is available and described in more detail in the following tactical patch. Please download and follow the instructions provided in the readme.txt to apply the patch:http://www.xilinx.com/txpatches/pub/applications/misc/ar43372.zip.

NOTE: This tactical patch is only compatible with ISE Design Suite 13.2. Use it with Initial ES Kintex-7 325T devices only. Behavioral simulations are not possible with the enhanced calibration algorithm as a result of the extended calibration run times.

Revision History
02/22/2012 - Updated to include ISE Design Suite 13.4
01/24/2012 - Updated to include EDK 13.4 details
10/12/2011 - Updated to include ISE Design Suite 13.3
09/19/2011 - Updated patch to revision 5

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A

Associated Answer Records

AR# 43372
Date 05/20/2012
Status Active
Type Known Issues
  • Kintex-7
  • MIG
  • MIG 7 Series
Page Bookmarked