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AR# 43383: 13.2 EDK - BSB Generated MHS parameters of AXI_V6_DDRx is incorrect for third party boards
13.2 EDK - BSB Generated MHS parameters of AXI_V6_DDRx is incorrect for third party boards
I am attempting to generate an AXI BSB system for Avnet V6LX130T board with DDR3 included. The generated MHS parameters for theAXI_V6_DDRx core seems to be incorrect.
The following describes the BSB behavior when the Avnet V6LX130T board is used in each implementation mode:
If the default "Area" is selected, BSB ignores the DDR3 parameter settings such as the DQ and DQS width from the Avnet V6LX130T XBD2 file and instead uses the parameters for the ML605 DDR3 interface in x8 mode.
In the "Area" mode, BSB sets the DDR3 address range for the Avnet board to 64 MB (Avnet board has 128 MB of DDR3 and this is specified in the XBD2 file).
If the "Throughput" option is selected, BSB uses the DDR3 parameters from V6LX130T XBD file. However, it sets the DDR3 address range for the Avnet board to the ML605 DDR3 address range which happens to be significantly larger than the memory on the Avnet board.
Also, in the "Throughput" mode, BSB sets the "C_S_AXI_DATA_WIDTH" parameter to 256, which happens to be the correct parameter for the ML605 x64 DDR3 memory interface, not the Avnet board x16 DDR3.