This maximumData/REFCLK ppm offset is specified by the Gigabit Ethernet spec at +/-200 ppm. This is also the maximum range for the Virtex-5 GTXCDR without 2nd Order Loop enabled; see Table 24 in the Virtex-6 FPGADC and Switching Characteristics Data Sheet (DS152):
The errors are caused by the fact that the Data/REFCLK ppm offset between the ML507 and the PC is outside of the maximum range.
This is due to frequency differences observed from the X7 oscillator on the board.
When this behavior occurs, the link can be made to work by enabling the 2nd Order Loop of the CDR which allows the system to handle a maximum frequency difference of up to +/-2000 ppm.
The 2nd Order Loop of the CDR can be enabled by changing the PMA_RX_CFG from25'0F44088 to25'0F44089.
This issue is confined to the ML507, and does not affect Virtex-5 devices in general.
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