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AR# 43420

Xilinx Serial Transceivers - Can the LVDS standard be used for reference clocks?


This answer record discusses the supported standards for reference clocks of transceivers.


LVPECL and LVDS are commonly used standards used for reference clocks in the industry.

Virtex-6 FPGA GTX Transceivers User Guide (UG366) (see Board Design Guidelines section) states that both LVPECL and LVDS standards are supported for transceiver reference clocks, but the Virtex-6 FPGA GTH Transceivers User Guide (UG371) does not recommend LVDS to be used for reference clocks because of minimum input signal amplitude reasons for the reference clock.

If the user can guarantee in their design that the LVDS reference clock will have adequate amplitude and meet the minimum input signal amplitude requirements (500 mVppdiff for <=600 MHz, 600 mVppdiff for > 600 MHz for Virtex-6 GTH Transceivers from DS152, http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf) in the data sheets for transceiver reference clocks, there should not be any problems in using LVDS standard for reference clock in the Virtex-6 GTH transceivers.

Similarly, for the 7 series FPGA family of transceivers, LVDS standard can be used if the input signal amplitude level requirements in the data sheets are met.

AR# 43420
Date 02/28/2013
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Virtex-6 HXT