This answer record highlights the important requirements and known issues for the Virtex-7 FPGA Initial Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 485T Initial ES FPGA devices (XC7V485T CES9937). Additional silicon limitations might exist, so reference the Initial ES errata (EN172) that accompanies the devices.
This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
Software Known Issues
All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on Initial ES FPGA devices is dependent on Xilinx hardware validation, whichis ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records section below for the most recent information. The list includes all Pre-production IP cores that have been hardware validated on Initial ES at this time:
This listis updated as hardware validation is completed.If there are further questions about hardware validation for a particular IP Core, please contact a Field Application Engineer.
IP Known Issues
Other Important Items
09/24/2012 - Minor update; no change to content
02/27/2012 - Updated software requirements to ISE 13.4 due to MIG requirements
02/06/2012 - Updated MIG 7 series information
01/23/2012 - Updated PCIe information
10/26/2011 - Updated for ISE 13.3 tools release
09/29/2011 - Consolidated all patches in one list in software section
08/24/2011 - Initial release