Description

This answer record highlights the important requirements and known issues for the Virtex-7 FPGA Initial Engineering Sample (ES) program related to software and IP. These items are specifically relevant to designs targeting the Virtex-7 485T Initial ES FPGA devices (XC7V485T CES9937). Additional silicon limitations might exist, so reference the Initial ES errata (EN172) that accompanies the devices.

This answer record is updated frequently as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.

Solution

Software Requirements

• ISE Design Suite 13.4, available on the Xilinx Download Center, is required for use of Initial ES silicon for Virtex-7 485T devices
• Patches - this is the complete list of available patches for ISE 13.4 design tools targeting Virtex-7 Initial ES silicon
  • Required Patches for all Users:
    • None
  • Required Patchesbased on usage:
    • (Xilinx Answer 45653)- Required patch if using MIG DDR2/DDR3 memory interface

Software Known Issues

• (Xilinx Answer 40905) - 13.x Software Known Issues Related to the 7 Series FPGAs

IP Requirements

All 7 Series IP Cores are listed as Pre-production in the CORE Generator "Status" field. Support of Pre-production cores on Initial ES FPGA devices is dependent on Xilinx hardware validation, whichis ongoing throughout the ES period. IP that has been hardware validated is still subject to change as verification and characterization work continues. Consult the IP Known Issues Answer Records section below for the most recent information. The list includes all Pre-production IP cores that have been hardware validated on Initial ES at this time:

• 7 Series Integrated Block for PCI Express
• MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II

This listis updated as hardware validation is completed.If there are further questions about hardware validation for a particular IP Core, please contact a Field Application Engineer.

IP Known Issues

• 7 Series Integrated Block for PCI Express
  • (Xilinx Answer 40469) 7 Series Integrated Block Wrapper for PCI Express - Release Notes and Known Issues
  • (Xilinx Answer 43243) Virtex-7/Kintex-7 FPGA XC7K325T CES9937 Integrated Block for PCI Express - Active State Power Management Not Supported for Gen 2 Rates
• MIG 7 Series DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II
  • MIG 7 Series users need to use MIG 7 Series v1.4 available with ISE Design Suite 13.4 or later due to updated calibration changes and CKE/ODT implementation changes as outlined in (Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified
  • (Xilinx Answer 45195) MIG 7 Series - Release Notes and Known Issues for all releases
  • Set the top level parameter "PART_REV" to "485t.1". This parameter should be set in "example_design/rtl/example_top.v" and "user_design/rtl/core_name.v." This parameter properly configures the PHASER_IN parameters for the Virtex-7 485T Initial Engineering Sample Devices.
  • If byte errors are seen after calibration where either bytes are skipped or added, the extended calibration should be enabled by setting the top-level parameter "XC7K325T_REV_1X" to "TRUE". This parameter should be set in "example_design/rtl/example_top.v" and "user_design/rtl/core_name.v".

Other Important Items

• (Xilinx Answer 43244) Kintex-7/Virtex-7 GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial ES Silicon

Revision History:

09/24/2012 - Minor update; no change to content
02/27/2012 - Updated software requirements to ISE 13.4 due to MIG requirements
02/06/2012 - Updated MIG 7 series information
01/23/2012 - Updated PCIe information
10/26/2011 - Updated for ISE 13.3 tools release
09/29/2011 - Consolidated all patches in one list in software section
08/24/2011 - Initial release

Linked Answer Records

Master Answer Records

Associated Answer Records