This section of the MIG Design Assistant focuses on the Controller Responsibilities of the Spartan-6 designs. The Memory Controller Block (MCB) is responsible for receiving all requests from the User Interface.In processing these requests, the MCB ensures that all functional and timing requirements of the JEDEC standard/memory device are met. The MCB only receives Read/Write commands, but must ensure that all required commands to complete Reads/Writes are sent (Refresh, Activate, Precharge).
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For information on available DDR Commands MIG Spartan-6 MCB, see: (Xilinx Answer 43357) - Available DDR Commands
For information on the Self-Refresh Counter for the MIG Spartan-6 MCB design, see: (Xilinx Answer 40737) - JEDEC Spec - Self-Refresh
For information on the Auto-Refresh Counter for the MIG Spartan-6 MCB design, see: (Xilinx Answer 34154) - What is the REFRESH period and how can it be changed?
For Information on how many commands can be stored at a time, see: (Xilinx Answer 43359) - User Interface - How many commands & data can be stored?