AR# 4345: FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted
FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted
Keyword: gsr, set flip-flop, verilog
Description: Example of a behavioral description of a preset and reset FF upon power-up using FPGA Compiler as the synthesis tool. This example is also incorperating a STARTUP block so that the global set/reset signal is brought out to a user pin.
Connect the STARTUP block to a port as well as to every FF in the design. By connecting the same port to all FF re/presets, the RTL testbench can match the Timing testbench in terms of the global reset. Map will issue the following expected warning:
WARNING:baste:22 - The signal "n110" is connected to the GR/GSR (global set/reset) pin on the STARTUP component as well as every asynchronous flip-flop set/reset in the design. Removing this signal from every flip-flop in the design (leaving the STARTUP connection) will reduce the amount of routing resources required to implement the design.
This is OK since we want that signal to be removed. Make sure to connect this signal to every inferred FF and Latch in the design or else the signal will not get removed and redundant routing will result.