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AR# 43459

13.2 EDK - CRT0.S is Improperly zero-ing out .bss and .sbss Sections


$XILINX_EDK/sw/lib/ppc405/src/xil-crt0.S contains latent errors in the parts which zero .bss and .sbss. The same error is repeated in the essentially identical code used to zero the two sections.

The error is latent, causing incorrect operation only if the byte count is a non-multiple of 4 and greater than 4, that is, only if a remainder of 1-3 bytes is zeroed following the zeroing of 1 or more words. This is because the result of the stwu instruction leaves the last address updated in R6, not the next word to be updated. Therefore, when "addi 6,6,-1" is reached, the address is adjusted to re-zero 1-3 bytes in the last full word zeroed, rather than the 1-3 bytes following that word.


To work around this, simply move one line and edit another, so your CRT0.s snippet is similar to below:
     /* clear sbss */      lwz 6,.Lsbss_start(5) /* calculate beginning of the SBSS */      lwz 7,.Lsbss_end(5)/* calculate end of the SBSS */       cmplw 1,6,7      bc 4,4,.Lenclsbss /* If no SBSS, no clearing required */       li 0,0 /* zero to clear memory */      subf 8,6,7 /* number of bytes to zero */      addi 6,6,-4 /* adjust so we can use stwu */ MOVED      srwi. 9,8,2 /* number of words to zero */      beq .Lstbyteloopsbss /* Check if the number of bytes was less than 4 */      mtctr 9 .Lloopsbss:      stwu 0,4(6) /* zero sbss */      bdnz .Lloopsbss  .Lstbyteloopsbss:      andi. 9,8,3 /* Calculate how many trailing bytes we have */      beq 0,.Lenclsbss      mtctr 9      addi 6,6,3 /* adjust appropriately for stbu */ // EDITED  .Lbyteloopsbss:      stbu 0,1(6)      bdnz .Lbyteloopsbss  .Lenclsbss: .Lstclbss: 
AR# 43459
Date 12/15/2012
Status Active
Type General Article
  • Virtex
  • Virtex QPro/R
  • Virtex-4 FX
  • More
  • Virtex-5 FXT
  • Virtex-II Pro
  • Virtex-II Pro X
  • Less