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AR# 43465

13.2 EDK, BSB - Why is the DDR3 DQ width set to 8 bits with my ML605 BSB generated project?


Why is the DQ set to 8 bits with my ML605 Base System Builder (BSB) generated project when the ML605 supports 64-bits?


By defaultBSB is set forarea optimization, which uses only 8-DQ bits to save resources. Because MIG uses a /4 controller architecture to support high SDRAM speeds, a 64-bit wide interface would result in a 256-bit wide AXI interface andAXI Interconnect datapaths, consuming logic resources.

For64-bit DDR3 DQ width, switch the BSB choice from 'Area' to 'Performance'.

AR# 43465
Date 12/15/2012
Status Active
Type General Article
  • EDK - 13.2
Boards & Kits
  • Virtex-6 FPGA ML605 Evaluation Kit
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