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AR# 43491

13.2 EDK, AXI_Interconnect - DECERR when accessing AXI4-Lite slaves from AXI4 masters


When a transaction is issued from a 64-bit AXI4 master to a 32-bit AXI4-Lite slave, the AXI Interconnect returns a DECERR response to the AXI4 master, potentially causing a processor exception or system hang.

How do I resolve this issue?


This DECERR is intended to be generated by the AXI Interconnect when an unsupported access to an AXI4-Lite slave occurs.

The AXI Interconnect data sheet, DS768 describes an AXI4-Lite access violation under either of the following conditions:

Burst length violation: Transaction length >1 data beat when targeting an AXI4-Lite slave device.
Data size violation: Transaction data transfer size wider than 4 bytes when targeting an AXI4-Lite slave device.

For example, a 64-bit wide AXI4 master issuing a 64-bit wide and single-cycle transaction to an AXI4-Lite slave will cause a DECERR since the interconnect cannot create a 2-cycle burst to an AXI4-Lite slave.

A 64-bit wide master can still issue a 32-bit wide transfer to an AXI4-Lite slave.

It is not necessary to enable any narrow burst parameters.

This AXI Interconnect limitation was chosen to achieve the lowest possible AXI4-Lite device utilization. 

The ARM AXI v2.0 specification does not require interconnect to translate between AXI4 and AXI4-Lite transactions.
AR# 43491
Date 10/02/2014
Status Active
Type General Article
  • AXI Interconnect
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