Data errors can be seen post calibration for many reasons. When a data error occurs, there are steps that should be followed to debug the cause of the error(s). This answer record focuses on the recommended steps to debug the root cause of data errors.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Isolating Data Errors
Isolate the Error:
Data errors in hardware can point to many different board level issues such as crosstalk or stuck bits. The first step in debugging a root cause for a data error, is to isolate the data error(s).
Determine if the error is due to the write or read:The root cause of a data error can come from either a write or a read. The next step is then to determine whether the memory device received incorrect data during a write, or if the data became corrupted on the read.
The Spartan-6 FPGA Memory Interface Solutions User Guide (UG416) includes a section on Data Errors in the Debug Guide; see the "Debugging MCB Designs" > "Isolating Bit Errors" section for more details on isolating the error and determining whether the error occurs during a write or read:http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_8/ug416.pdf
For additional information on isolating the write versus the read causing problems, see (Xilinx Answer 43540).
Test board with different data patterns using the Traffic Generator:
MIG includes a Traffic Generator with the provided Example Design that can be used to help isolate data errors. The traffic generator can be configured to send many different traffic patterns that test for different board issues. For example, sending a "hammer" pattern with switching ones and zeros will stress SSO while sending "PRBS" tests more real world patterns. For more information on the traffic generator and how to configure it to test different data patters, see (Xilinx Answer 43541).
Small Data Valid Window
Data errors can also be seen when a small data valid window was found during calibration.This is because during normal operation, the data patterns will be "tougher" causing a smaller eye due to more logic switching.This results in more switching related noise.
Adherence to the Spartan-6 MCB MIG board layout guidelines ensures a proper data valid is found during calibration.However, not following the guidelines can result in either calibration failures or a small data valid window.It is important to go through a general hardware debug flow and verify the MIG guidelines have been followed.
For general board level debug, see (Xilinx Answer 43520).
To calculate the read data valid window post calibration, see (Xilinx Answer 42172).
For information on the Spartan-6 MCB MIG Board Layout Guidelines, see the following:
For information on debugging calibration failures, see (Xilinx Answer 43537).