We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43539

MIG Spartan-6 MCB - Usage of Debug Port


The MIG Spartan-6 MCB design includes an option to generate the core with a debug port. Enabling the debug port provides the ability to view the behavior during hardware operation of common debug signals through the ChipScope tool. To enable the debug port, turn the Debug Signals for Memory Controller option to ON. This option is available on the FPGA Options screen of the MIG tool. Once the design is generated with this option enabled, generate a bitstream with the provided Example Design using the "ise_flow.bat" script file located in the output "example_design/par" directory. Running the Example Design with the debug port is the first step in any hardware debug. This is a known working design which can be configured to test for many different signal integrity issues.

This Answer Record provides useful information on using the debug port to correct specific types of problems such as calibration failures and bit errors.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


  1. Once the design is implemented and a bitstream is available, open the ChipScope analyzer and configure the device.
  2. Open the provided ChipScope project; example_design\par\example_top.cdc.
  3. The Example Design with the Debug Port is now running in your system. You can now trigger off of different signals to view the behavior and test for different problems.
Signals/Parameters of Interest:

The data signals assigned in the debug port include the command path, write datapath, and read datapath signals as defined in the "Interface Details" section of the Spartan-6 FPGA Memory Controller User Guide (UG388):

The trigger signals assigned in the trigger port include the calib_done and error (example_design only) signals. The trigger can be asserted separately on calib_done to debug calibration failures and error to debug data errors after calibration.

The Debug Port is enabled through the top-level RTL parameter DEBUG_PORT. Setting this to ON enables the port in the RTL. Additionally, CORE Generator interface command lines are required in the "ise_flow.bat" script file to generate the necessary cores to run in the ChipScope analyzer.

Using the Debug Port to Isolate a Write versus Read Problem:

Linked Answer Records

Associated Answer Records

AR# 43539
Date 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • MIG