You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
4.2i Foundation - I am unable to synthesize or add an ABEL file to an HDL project
Keywords: ABEL, HDL, synthesize, top level, grayed out, not highlighted
I cannot add an ABEL file to my project in Project Manager, and the "ABEL" language selection is grayed out.
1 If you wish to create a top-level ABEL design, you must do this in a "Schematic" project flow.
Please see (Xilinx Answer 4353) for more information on this process.
2 If you wish to include an ABEL file in a top-level VHDL or Verilog design, you must instantiate the ABEL module as a black-box in the VHDL or Verilog.
First, the ABEL file must be synthesized to an EDIF file; this EDIF file is then instantiated as the black box in the top-level VHDL or Verilog.
Was this Answer Record helpful?