UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43559

MIG Virtex-6 DDR2/DDR3 - Generating a Reference clk from an Existing MMCM Resource

Description

The Virtex-6 DDR2/DDR3 MIG design has two clock inputs: the reference clock and the system clock input. 

The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks (used in the user interface, controller, and PHY layers) and drives the MMCM instantiated in the infrastructure module. 

The reference clock can be generated from the existing MMCM resource instead of driving it from an external clock source.

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243)

The Xilinx MIG Solution Center is available to address all questions related to MIG.

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

To generate the reference clock internally from a single clock source, perform the following steps:

  1. The RTL files that have to be changed for this requirement are Design top module (example_top or user design top), infrastructure, and iodelayctrl.
     
  2. Before making the changes to the RTL, invoke the Clocking Wizard from the CORE Generator interface and provide the source clock frequency.
    Also, configure the Clocking Wizard to generate four outputs; three outputs are required for the MIG default design, and the fourth output as idelayctrl reference clock (200 MHz or 300 MHz). 
    Make a note of the generated multiplication factor (CLKFBOUT_MULT_F), divide factor (DIVCLK_DIVIDE), and respective clock output divide factor (CLOCKn_DIVIDE).
     
  3. Module infrastructure changes:
    1. An additional new parameter should be added for the fourth clock output, which would take the value of CLOCK3_DIVIDE; name this parameter as CLKOUT3_DIVIDE.
      Also, pass this parameter to the CLKOUT3_DIVIDE parameter of the MMCM instance (or) the CLKOUT3_DIVIDE parameter value can be directly mapped to the CLKOUT3_DIVIDE parameter of the MMCM instance in the infrastructure module.
    2. In the "infrastructure.v" file, add an additional output port as clk_ref, which is a 200 MHz or 300 MHz clock generated from MMCM.
      This should be connected to the CLKOUT3 port of the MMCM.
      This clock drives the iodelayctrl module.
    3. Add an additional output port to bring the pll_lock signal out of the infrastructure module.
      When a PLL drives the idelayctrl block, this pll_lock needs to be incorporated in the idelayctrl reset in the iodelay_ctrl module.
       
  4. Module iodelayctrl changes:
    1. The MMCM generates the idelayctrl reference clock; therefore, BUFG can drive the reference clock.
      For this reason, replace the clk_ref_ibufg signal with clk_ref.
       
      BUFG u_bufg_clk_ref
      (
      .O (clk_ref_bufg),
      .I (clk_ref)
      );
    2. Add an additional input port to bring in the pll_lock signal from the infrastructure module's MMCM.
    3. Incorporate the pll_lock into the idelayctrl reset as directed by the comments in iodelay_ctrl.v/vhd:
       

      // Add PLL lock if PLL drives IDELAYCTRL in user design

      assign rst_tmp_idelay = sys_rst_act_hi or (not pll_lock);

    4. Comment out the part of the code between the generate and endgenerate statements.
      The logic includes the handling of single or differential ended clock input and provides buffers for the same.
       
  1. Design Top Module changes (example_top.v or user design top):
    1. Replace the parameter values of CLKFBOUT_MULT_F, DIVCLK_DIVIDE, and CLKOUT_DIVIDE with the newly generated factors.
      Please note that the CLKOUT_DIVIDE parameter should have the value of CLOCK0_DIVIDE generated by the Clocking Wizard.
    2. Comment out the reference clock ports (clk_ref_p and clk_ref_n for DIFFERENTIAL mode and clk_ref for SINGLE_ENDED mode) in the top-level input ports and declare them as wire.
      Mapping of the reference clock generated from the infrastructure module to the iodelayctrl instance port should also be performed.
    3. Add the pll_lock ports for the infrastructure and iodelay_ctrl modules and connect the two.
       
  2. UCF Changes:
    1. The MMCM generates the idelayctrl reference clock, so no idelayctrl clock constraints are necessary in the UCF.
      Therefore, comment out the idelayctrl reference clock constraints in UCF.

Note:

(1) Input clock frequency is the same as memory controller frequency for all Virtex-6 designs.
So when clocking wizard is invoked, reference clock frequency of 200 MHz or 300 MHz might not be generated for various input frequencies.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35242 MIG Virtex-6 DDR2/DDR3 - Clock Requirements and Modifying the Input Clock Frequency N/A N/A
AR# 43559
Date Created 08/11/2011
Last Updated 03/31/2015
Status Active
Type General Article
IP
  • MIG