ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
pair have been found that are not placed at a routable site pair.
The driverBUFGCTRL component <user_clock/clkout2_buf> is placed at site<BUFGCTRL_X0Y0>.
The load BUFGCTRL component<U_FUSB300/U_FUSB300_CLKRST/aux_clk_bufg> is placed at site<BUFGCTRL_X0Y31>.
The BUFGCTRL components can use the fast path between them
if they are placed in adjacent BUFGCTRL sites, and both are in the samehalf of the device (TOP or BOTTOM).
You may want to analyze why this problemexists and correct it.
This placement is UNROUTABLE in PAR and therefore,this error condition should be fixed in your design.
You may use theCLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to
a WARNING in order to generate an NCD file. This NCD file can then be used
in FPGA Editor to debug the problem. A list of all the COMP.PINS used in
this clock placement rule is listed below. These examples can be used
directly in the .ucf file to demote this ERROR to a WARNING.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.