General Description: In Foundation F1.5, top-level VHDL or Verilog designs are created as "HDL Flow" projects. When in the "HDL Flow," the VHDL or Verilog files in the project are edited and syntax-checked in the HDL Editor, but are not synthesized from within the HDL Editor. This behavior is different from Foundation F1.4 and earlier.
To synthesize the HDL file(s) in Foundation F1.5, you have the following choices:
1. Click the Synthesis phase button in the project flowchart in the Project Manager. 2. Right-click on the HDL entity/module in the Files tab, and choose "Synthesize". 3. Select Synthesis --> Synthesize from the Project Manager.
For VHDL or Verilog modules in a schematic top-level project, synthesize the HDL files from within the HDL Editor by selecting Synthesis-->Synthesize, or Project --> Create Macro.
In order to be able to synthesize the HDL file by using the Synthesis button in the Project Manager, the HDL file must be added to the Foundation Project. Once it is added, you should be able to see it in the Files tab of the Project Manager. To add a file to the project, select Document -> Add from the Project Manager.