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AR# 43664

MIG Spartan-6 MCB - DDR SDRAM Initialization

Description

The MIG Spartan-6 MCB design's first stage of initialization and calibration is to complete the required SDRAM initialization sequence as defined by the Jedec Standard.

NOTE:This Answer Record is a part of the Xilinx MIG Solution Center(Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Mode Registers

Each SDRAM has a series of mode registers, accessed via mode register set (MRS) commands. These mode registers determine various SDRAM behaviors, such as burst length, read and write CAS latency, and additive latency. The particular bit values programmed into these registers are configurable through the MIG GUI on the Memory Options screen. These GUI settings properly set top-level HDL parameters in the MIG output. These parameters should not be modified manually. Please rerun the MIG tool to change a mode register setting.

AR# 43664
Date Created 08/24/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG