The Spartan-6 MIG MCB design is supported as it is output from the CORE Generator tool with no modifications.
Xilinx does not support using the MCB PHY standalone only.
Additionally, Xilinx does not provide the timing requirements for the memory controller to PHY interface.
However, there is a DDR/DDR2 SDRAM soft PHY core available that was developed by Northwest Logic for distribution by Xilinx.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243)
The Xilinx MIG Solution Center is available to address all questions related to MIG.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The Spartan-6 FPGA DDR/DDR2 SDRAM soft PHY core was developed by Northwest Logic for distribution by Xilinx.
This reference design core was designed to meet the needs of customers who have custom or legacy DDR/DDR2 controllers and require just the physical interface (PHY) solution for Spartan-6 devices.
For more information, please contact Northwest Logic.