The documentation for the Virtex 6 built-in FIFO states that FWFT is not supported in common clock, synchronous mode.
However, when I generate the FIFO Generator Core in CORE Generator the option is there to select FWFT in common clock mode.
In FPGA Editor, the FWFT option is not enabled for the FIFO primitive.
Is FWFT really not supported in the built-in FIFOs of the Virtex 6 device?
The hard FIFO macro does not support FWFT for common clock mode. However, the FIFO Generator does.
In this case, the configuration is common clock built-in FIFO with FWFT, and FIFO generator builds the FWFT logic in the fabric.