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AR# 43747

Kintex-7, ChipScope Pro IBERT (13.2 and later) - IBERT wizard allows use of unsupported line rates with the QPLL for Initial Engineering Sample Silicon


The Kintex-7 FPGA IBERT GTX core allows the use of some line rates that are not supported for the QPLL when using Engineering Sample (ES) silicon. This answer record details this known issue and provides guidance on how to proceed if using this core and targeting Initial ES silicon.


For the Kintex-7 Lab ES and Initial ES silicon, the QPLL VCO frequency range only supports 5.93 - 6.6 GHz. The Kintex-7 FPGAIBERT GTX core only limits line rates based on the data sheet specifications. The Kintex-7 FPGA IBERT GTX core does not limit line rate selections to match the above limitation, so it is possible to enter an unsupported line rate for the QPLL when using initial ES silicon.

Make sure that the QPLL is not used outside the VCO frequency range of 5.93-6.6 GHz in the Kintex-7 Lab ES or Initial ES silicon. If the IBERT core targeting initial ES or ES Lab silicon is used outside of this range, this might result in unreliable behavior of the transceiver.

If it is unclear on whether the device that is targeted is subject to this limitation, please refer to (Xilinx Answer 37579)for instructions on how to readback the JTAG IDCODE for the device. Refer to the JTAG IDCODE section of the answer record. For the Kintex-7 325T, a JTAG ID of 0, 1, or 2 will have this limitation. For the Kintex-7 480T, only a JTAG ID of 0 will have this limitation.

AR# 43747
Date 01/02/2013
Status Active
Type Known Issues
  • Kintex-7
  • ChipScope Pro - 13.2
  • ChipScope Pro - 13.3