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Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System: http://www.xilinx.com/support/myalerts.
This Design Advisory covers the Spartan-6 FPGA SP601 Evaluation Kit, including critical issues with the reference design delivered with the kit.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
43987 | Xilinx Boards and Kits Solution Center - Design Advisories | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
45011 | Design Advisory for Spartan-6 - BUFPLL LOCK output always high in Bank 2 | N/A | N/A |
36291 | MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration | N/A | N/A |
AR# 43769 | |
---|---|
Date | 09/25/2012 |
Status | Active |
Type | Design Advisory |
Boards & Kits |