UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 43769: Design Advisory Master Answer Record for Spartan-6 FPGA SP601 Evaluation Kit

AR# 43769

Design Advisory Master Answer Record for Spartan-6 FPGA SP601 Evaluation Kit

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System: http://www.xilinx.com/support/myalerts.

This Design Advisory covers the Spartan-6 FPGA SP601 Evaluation Kit, including critical issues with the reference design delivered with the kit.

Solution

(Xilinx Answer 36291) - MIG, MPMC, Spartan-6 MCB -Memory failures occur on initial configuration
(Xilinx Answer 45011) - Design Advisory for Spartan-6 - BUFPLL LOCK output always high in Bank 2

Revision History
09/25/2012 - Minor update; no change to content
12/13/2011 - Answer Record 45011 added
09/13/2011 - Minor edit to title
08/09/2011 - Initial Release with Answer Record 36291

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43987 Xilinx Boards and Kits Solution Center - Design Advisories N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45011 Design Advisory for Spartan-6 - BUFPLL LOCK output always high in Bank 2 N/A N/A
36291 MIG, MPMC, Spartan-6 MCB - Memory failures occur on initial configuration N/A N/A
AR# 43769
Date 09/25/2012
Status Active
Type Design Advisory
Boards & Kits
  • Spartan-6 FPGA SP601 Evaluation Kit
Page Bookmarked