We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43782

13.2 XST - How to Instantiate a Verilog Module in a VHDL Project


I am seeing some errors in NGDBuild where a Verilog module is not found during Translate.

"Checking expanded design ...

ERROR:NgdBuild:604 - logical block 'paththru/hierarchy/module_i' with type 'module' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'module' is not supported in target 'virtex6'."

After reviewing the XST report, I noticed that a "module" was not bound successfully, and therefore,was a black box.


This is a known issue in XST and a CR has been filed. Use any of the following three work-arounds to avoid this problem:

  1. Ensure that the VHDL block containing the Verilog module has a library association "work" that is the same as the Verilog module.
  2. Individually wrap the Verilog module with a VHDL wrapper. Instantiate this VHDL wrapper in the VHDL project. Also, avoid performing this wrapping functionality in a higher level of hierarchy (for example, in the top level of the design). XST does not bind the ports correctly when this method is used.
  3. Synthesize the Verilog module standalone and add the resulting NGC file to the project.
AR# 43782
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
Page Bookmarked