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AR# 43792

13.2 Virtex-7/ Kintex-7 - Timing: Switching Limit Error for OSERDES


When Running Timing Analysis on an OSERDES block, the following switching limit error displays:

Component Switching Limit Checks:
NET "clk" PERIOD = 1.60771704 ns HIGH 50%;


Slack: -0.113ns (period - min period limit)
Period: 1.607ns
Min period limit: 1.720ns (581.395MHz) (Tosper_CLK)
Physical resource: inst_DAC/OUT.oserdese2_master/CLK
Logical resource: inst_DAC/OUT.oserdese2_master/CLK
Location pin: OLOGIC_X0Y280.CLK
Clock network: inst_DAC/clk

Is this a valid error, even though it contradicts with the data sheet?


This switching limit error is incorrect and this will be updated in a later version of the software. The workaround is to refer to the valid switching limits of the OSERDES block in the data sheet.
AR# 43792
Date 10/18/2011
Status Archive
Type General Article
  • Virtex-7
  • Virtex-7 HT
  • Kintex-7
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
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