AR# 438

SYNOPSYS - XNFPREP issues ERROR 3673, due to multiple clock buffers inserted.

Description

Keywords: Synopsys, XNFPREP, Error3673, global buffers

Urgency: Standard

General Description:
The FPGA Compiler and the Design Compiler are capable of automatically inserting global buffers (BUFG) on clock nets and high fan-out nets. However, a problem lies in the number of global buffers that get inserted, as the compiler may insert more
global buffers than are available on the device. This causes XNFPREP to terminate with Error Message 3673.

Solution

To avoid the excessive use of global buffers on clock nets, explicitly define which ports are clock ports. Do this by declaring that all ports are "not clock" ports; then, define which ports are indeed clock ports.

In a script file or on the command line, type:

set_pad_type -no_clock all_inputs()
set_pad_type -clock {clk1,clk2,sig1}

where clk1, clk2 and sig1 are the clock nets used in this example. Replace these signal names with the actual names in your design.

You might get the following warning from Synopsys:

Warning: I/O pad attribute mismatch on port 'generic_input' (OPT-1014)

This is not a problem. An IBUF will be used for the non-clock ports.

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AR# 438
Date	06/21/2001
Status	Archive
Type	General Article

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